module CLK_DIV (
    input  wire clk,
    input  wire rst_n,

    input  wire[31:0] div,
    output reg        clk_out,
    output reg        locked  
);

reg[31:0] counter;

always @(posedge clk or negedge rst_n) begin
    if (!rst_n) begin
        counter <= 0;
        locked <= 0;
        clk_out <= 0;
    end else begin
        if (counter > div) begin
            clk_out <= ~clk_out;
            locked <= 1;
            counter <= 0;
        end else begin
            clk_out <= clk_out;
            locked <= locked;
            counter <= counter + 1;
        end
    end
end

endmodule //CLK_DIV